Line data Source code
1 : //===-- R600RegisterInfo.cpp - R600 Register Information ------------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : /// \file
11 : /// R600 implementation of the TargetRegisterInfo class.
12 : //
13 : //===----------------------------------------------------------------------===//
14 :
15 : #include "R600RegisterInfo.h"
16 : #include "AMDGPUTargetMachine.h"
17 : #include "R600Defines.h"
18 : #include "R600InstrInfo.h"
19 : #include "R600MachineFunctionInfo.h"
20 : #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
21 :
22 : using namespace llvm;
23 :
24 291 : R600RegisterInfo::R600RegisterInfo() : R600GenRegisterInfo(0) {
25 291 : RCW.RegWeight = 0;
26 291 : RCW.WeightLimit = 0;
27 291 : }
28 :
29 : #define GET_REGINFO_TARGET_DESC
30 : #include "R600GenRegisterInfo.inc"
31 :
32 4594 : BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
33 4594 : BitVector Reserved(getNumRegs());
34 :
35 4594 : const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>();
36 : const R600InstrInfo *TII = ST.getInstrInfo();
37 :
38 4594 : reserveRegisterTuples(Reserved, R600::ZERO);
39 4594 : reserveRegisterTuples(Reserved, R600::HALF);
40 4594 : reserveRegisterTuples(Reserved, R600::ONE);
41 4594 : reserveRegisterTuples(Reserved, R600::ONE_INT);
42 4594 : reserveRegisterTuples(Reserved, R600::NEG_HALF);
43 4594 : reserveRegisterTuples(Reserved, R600::NEG_ONE);
44 4594 : reserveRegisterTuples(Reserved, R600::PV_X);
45 4594 : reserveRegisterTuples(Reserved, R600::ALU_LITERAL_X);
46 4594 : reserveRegisterTuples(Reserved, R600::ALU_CONST);
47 4594 : reserveRegisterTuples(Reserved, R600::PREDICATE_BIT);
48 4594 : reserveRegisterTuples(Reserved, R600::PRED_SEL_OFF);
49 4594 : reserveRegisterTuples(Reserved, R600::PRED_SEL_ZERO);
50 4594 : reserveRegisterTuples(Reserved, R600::PRED_SEL_ONE);
51 4594 : reserveRegisterTuples(Reserved, R600::INDIRECT_BASE_ADDR);
52 :
53 588032 : for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
54 592626 : E = R600::R600_AddrRegClass.end(); I != E; ++I) {
55 588032 : reserveRegisterTuples(Reserved, *I);
56 : }
57 :
58 4594 : TII->reserveIndirectRegisters(Reserved, MF, *this);
59 :
60 4594 : return Reserved;
61 : }
62 :
63 : // Dummy to not crash RegisterClassInfo.
64 : static const MCPhysReg CalleeSavedReg = R600::NoRegister;
65 :
66 22819 : const MCPhysReg *R600RegisterInfo::getCalleeSavedRegs(
67 : const MachineFunction *) const {
68 22819 : return &CalleeSavedReg;
69 : }
70 :
71 2416 : unsigned R600RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
72 2416 : return R600::NoRegister;
73 : }
74 :
75 404862 : unsigned R600RegisterInfo::getHWRegChan(unsigned reg) const {
76 809724 : return this->getEncodingValue(reg) >> HW_CHAN_SHIFT;
77 : }
78 :
79 206170 : unsigned R600RegisterInfo::getHWRegIndex(unsigned Reg) const {
80 412340 : return GET_REG_INDEX(getEncodingValue(Reg));
81 : }
82 :
83 1 : const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
84 : MVT VT) const {
85 : switch(VT.SimpleTy) {
86 : default:
87 1 : case MVT::i32: return &R600::R600_TReg32RegClass;
88 : }
89 : }
90 :
91 461371 : const RegClassWeight &R600RegisterInfo::getRegClassWeight(
92 : const TargetRegisterClass *RC) const {
93 461371 : return RCW;
94 : }
95 :
96 46282 : bool R600RegisterInfo::isPhysRegLiveAcrossClauses(unsigned Reg) const {
97 : assert(!TargetRegisterInfo::isVirtualRegister(Reg));
98 :
99 : switch (Reg) {
100 : case R600::OQAP:
101 : case R600::OQBP:
102 : case R600::AR_X:
103 : return false;
104 : default:
105 : return true;
106 : }
107 : }
108 :
109 0 : void R600RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
110 : int SPAdj,
111 : unsigned FIOperandNum,
112 : RegScavenger *RS) const {
113 0 : llvm_unreachable("Subroutines not supported yet");
114 : }
115 :
116 660200 : void R600RegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
117 660200 : MCRegAliasIterator R(Reg, this, true);
118 :
119 1342536 : for (; R.isValid(); ++R)
120 : Reserved.set(*R);
121 660200 : }
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