Line data Source code
1 : //===- RegisterClassInfo.cpp - Dynamic Register Class Info ----------------===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file implements the RegisterClassInfo class which provides dynamic
11 : // information about target register classes. Callee-saved vs. caller-saved and
12 : // reserved registers depend on calling conventions and other dynamic
13 : // information, so some things cannot be determined statically.
14 : //
15 : //===----------------------------------------------------------------------===//
16 :
17 : #include "llvm/CodeGen/RegisterClassInfo.h"
18 : #include "llvm/ADT/ArrayRef.h"
19 : #include "llvm/ADT/BitVector.h"
20 : #include "llvm/ADT/SmallVector.h"
21 : #include "llvm/CodeGen/MachineFunction.h"
22 : #include "llvm/CodeGen/MachineRegisterInfo.h"
23 : #include "llvm/CodeGen/TargetFrameLowering.h"
24 : #include "llvm/CodeGen/TargetRegisterInfo.h"
25 : #include "llvm/CodeGen/TargetSubtargetInfo.h"
26 : #include "llvm/MC/MCRegisterInfo.h"
27 : #include "llvm/Support/CommandLine.h"
28 : #include "llvm/Support/Debug.h"
29 : #include "llvm/Support/raw_ostream.h"
30 : #include <algorithm>
31 : #include <cassert>
32 : #include <cstdint>
33 :
34 : using namespace llvm;
35 :
36 : #define DEBUG_TYPE "regalloc"
37 :
38 : static cl::opt<unsigned>
39 : StressRA("stress-regalloc", cl::Hidden, cl::init(0), cl::value_desc("N"),
40 : cl::desc("Limit all regclasses to N registers"));
41 :
42 : RegisterClassInfo::RegisterClassInfo() = default;
43 :
44 1329269 : void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) {
45 : bool Update = false;
46 1329269 : MF = &mf;
47 :
48 : // Allocate new array the first time we see a new target.
49 1329269 : if (MF->getSubtarget().getRegisterInfo() != TRI) {
50 116727 : TRI = MF->getSubtarget().getRegisterInfo();
51 10104665 : RegClass.reset(new RCInfo[TRI->getNumRegClasses()]);
52 : Update = true;
53 : }
54 :
55 : // Does this MF have different CSRs?
56 : assert(TRI && "no register info set");
57 :
58 : // Get the callee saved registers.
59 1329269 : const MCPhysReg *CSR = MF->getRegInfo().getCalleeSavedRegs();
60 1329269 : if (Update || CSR != CalleeSavedRegs) {
61 : // Build a CSRAlias map. Every CSR alias saves the last
62 : // overlapping CSR.
63 124729 : CalleeSavedAliases.resize(TRI->getNumRegs(), 0);
64 2166027 : for (const MCPhysReg *I = CSR; *I; ++I)
65 28698133 : for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI)
66 53313664 : CalleeSavedAliases[*AI] = *I;
67 :
68 : Update = true;
69 : }
70 1329269 : CalleeSavedRegs = CSR;
71 :
72 : // Different reserved registers?
73 1329269 : const BitVector &RR = MF->getRegInfo().getReservedRegs();
74 1329269 : if (Reserved.size() != RR.size() || RR != Reserved) {
75 : Update = true;
76 136517 : Reserved = RR;
77 : }
78 :
79 : // Invalidate cached information from previous function.
80 1192752 : if (Update) {
81 139259 : unsigned NumPSets = TRI->getNumRegPressureSets();
82 139259 : PSetLimits.reset(new unsigned[NumPSets]);
83 : std::fill(&PSetLimits[0], &PSetLimits[NumPSets], 0);
84 139259 : ++Tag;
85 : }
86 1329269 : }
87 :
88 : /// compute - Compute the preferred allocation order for RC with reserved
89 : /// registers filtered out. Volatile registers come first followed by CSR
90 : /// aliases ordered according to the CSR order specified by the target.
91 511783 : void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
92 : assert(RC && "no register class given");
93 1023566 : RCInfo &RCI = RegClass[RC->getID()];
94 :
95 : // Raw register count, including all reserved regs.
96 : unsigned NumRegs = RC->getNumRegs();
97 :
98 511783 : if (!RCI.Order)
99 242885 : RCI.Order.reset(new MCPhysReg[NumRegs]);
100 :
101 : unsigned N = 0;
102 : SmallVector<MCPhysReg, 16> CSRAlias;
103 511783 : unsigned MinCost = 0xff;
104 : unsigned LastCost = ~0u;
105 : unsigned LastCostChange = 0;
106 :
107 : // FIXME: Once targets reserve registers instead of removing them from the
108 : // allocation order, we can simply use begin/end here.
109 511783 : ArrayRef<MCPhysReg> RawOrder = RC->getRawAllocationOrder(*MF);
110 12861901 : for (unsigned i = 0; i != RawOrder.size(); ++i) {
111 12350118 : unsigned PhysReg = RawOrder[i];
112 : // Remove reserved registers from the allocation order.
113 12350118 : if (Reserved.test(PhysReg))
114 2162757 : continue;
115 20374722 : unsigned Cost = TRI->getCostPerUse(PhysReg);
116 10187361 : MinCost = std::min(MinCost, Cost);
117 :
118 10187361 : if (CalleeSavedAliases[PhysReg])
119 : // PhysReg aliases a CSR, save it for later.
120 1842058 : CSRAlias.push_back(PhysReg);
121 : else {
122 8345303 : if (Cost != LastCost)
123 : LastCostChange = N;
124 16690606 : RCI.Order[N++] = PhysReg;
125 : LastCost = Cost;
126 : }
127 : }
128 511783 : RCI.NumRegs = N + CSRAlias.size();
129 : assert(RCI.NumRegs <= NumRegs && "Allocation order larger than regclass");
130 :
131 : // CSR aliases go after the volatile registers, preserve the target's order.
132 2353841 : for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) {
133 1842058 : unsigned PhysReg = CSRAlias[i];
134 1842058 : unsigned Cost = TRI->getCostPerUse(PhysReg);
135 1842058 : if (Cost != LastCost)
136 : LastCostChange = N;
137 3684116 : RCI.Order[N++] = PhysReg;
138 : LastCost = Cost;
139 : }
140 :
141 : // Register allocator stress test. Clip register class to N registers.
142 511783 : if (StressRA && RCI.NumRegs > StressRA)
143 63 : RCI.NumRegs = StressRA;
144 :
145 : // Check if RC is a proper sub-class.
146 511783 : if (const TargetRegisterClass *Super =
147 511783 : TRI->getLargestLegalSuperClass(RC, *MF))
148 511783 : if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
149 120018 : RCI.ProperSubClass = true;
150 :
151 511783 : RCI.MinCost = uint8_t(MinCost);
152 511783 : RCI.LastCostChange = LastCostChange;
153 :
154 : LLVM_DEBUG({
155 : dbgs() << "AllocationOrder(" << TRI->getRegClassName(RC) << ") = [";
156 : for (unsigned I = 0; I != RCI.NumRegs; ++I)
157 : dbgs() << ' ' << printReg(RCI.Order[I], TRI);
158 : dbgs() << (RCI.ProperSubClass ? " ] (sub-class)\n" : " ]\n");
159 : });
160 :
161 : // RCI is now up-to-date.
162 511783 : RCI.Tag = Tag;
163 511783 : }
164 :
165 : /// This is not accurate because two overlapping register sets may have some
166 : /// nonoverlapping reserved registers. However, computing the allocation order
167 : /// for all register classes would be too expensive.
168 357314 : unsigned RegisterClassInfo::computePSetLimit(unsigned Idx) const {
169 : const TargetRegisterClass *RC = nullptr;
170 : unsigned NumRCUnits = 0;
171 32712418 : for (const TargetRegisterClass *C : TRI->regclasses()) {
172 32355104 : const int *PSetID = TRI->getRegClassPressureSets(C);
173 226939995 : for (; *PSetID != -1; ++PSetID) {
174 198407099 : if ((unsigned)*PSetID == Idx)
175 : break;
176 : }
177 32355104 : if (*PSetID == -1)
178 : continue;
179 :
180 : // Found a register class that counts against this pressure set.
181 : // For efficiency, only compute the set order for the largest set.
182 3822208 : unsigned NUnits = TRI->getRegClassWeight(C).WeightLimit;
183 3822208 : if (!RC || NUnits > NumRCUnits) {
184 : RC = C;
185 : NumRCUnits = NUnits;
186 : }
187 : }
188 357314 : compute(RC);
189 714628 : unsigned NReserved = RC->getNumRegs() - getNumAllocatableRegs(RC);
190 357314 : return TRI->getRegPressureSetLimit(*MF, Idx) -
191 357314 : TRI->getRegClassWeight(RC).RegWeight * NReserved;
192 : }
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