Line data Source code
1 : //===- MC/MCRegisterInfo.h - Target Register Description --------*- C++ -*-===//
2 : //
3 : // The LLVM Compiler Infrastructure
4 : //
5 : // This file is distributed under the University of Illinois Open Source
6 : // License. See LICENSE.TXT for details.
7 : //
8 : //===----------------------------------------------------------------------===//
9 : //
10 : // This file describes an abstract interface used to get information about a
11 : // target machines register file. This information is used for a variety of
12 : // purposed, especially register allocation.
13 : //
14 : //===----------------------------------------------------------------------===//
15 :
16 : #ifndef LLVM_MC_MCREGISTERINFO_H
17 : #define LLVM_MC_MCREGISTERINFO_H
18 :
19 : #include "llvm/ADT/DenseMap.h"
20 : #include "llvm/ADT/iterator_range.h"
21 : #include "llvm/MC/LaneBitmask.h"
22 : #include <cassert>
23 : #include <cstdint>
24 : #include <utility>
25 :
26 : namespace llvm {
27 :
28 : /// An unsigned integer type large enough to represent all physical registers,
29 : /// but not necessarily virtual registers.
30 : using MCPhysReg = uint16_t;
31 :
32 : /// MCRegisterClass - Base class of TargetRegisterClass.
33 : class MCRegisterClass {
34 : public:
35 : using iterator = const MCPhysReg*;
36 : using const_iterator = const MCPhysReg*;
37 :
38 : const iterator RegsBegin;
39 : const uint8_t *const RegSet;
40 : const uint32_t NameIdx;
41 : const uint16_t RegsSize;
42 : const uint16_t RegSetSize;
43 : const uint16_t ID;
44 : const int8_t CopyCost;
45 : const bool Allocatable;
46 :
47 : /// getID() - Return the register class ID number.
48 : ///
49 183140904 : unsigned getID() const { return ID; }
50 :
51 : /// begin/end - Return all of the registers in this class.
52 : ///
53 0 : iterator begin() const { return RegsBegin; }
54 8942414 : iterator end() const { return RegsBegin + RegsSize; }
55 :
56 : /// getNumRegs - Return the number of registers in this class.
57 : ///
58 2719767 : unsigned getNumRegs() const { return RegsSize; }
59 :
60 : /// getRegister - Return the specified register in the class.
61 : ///
62 0 : unsigned getRegister(unsigned i) const {
63 : assert(i < getNumRegs() && "Register number out of range!");
64 1018178 : return RegsBegin[i];
65 : }
66 :
67 : /// contains - Return true if the specified register is included in this
68 : /// register class. This does not include virtual registers.
69 0 : bool contains(unsigned Reg) const {
70 724397434 : unsigned InByte = Reg % 8;
71 724397434 : unsigned Byte = Reg / 8;
72 723335199 : if (Byte >= RegSetSize)
73 0 : return false;
74 382890843 : return (RegSet[Byte] & (1 << InByte)) != 0;
75 : }
76 :
77 : /// contains - Return true if both registers are in this class.
78 2610498 : bool contains(unsigned Reg1, unsigned Reg2) const {
79 4264579 : return contains(Reg1) && contains(Reg2);
80 : }
81 :
82 : /// getCopyCost - Return the cost of copying a value between two registers in
83 : /// this class. A negative number means the register class is very expensive
84 : /// to copy e.g. status flag register classes.
85 231762 : int getCopyCost() const { return CopyCost; }
86 :
87 : /// isAllocatable - Return true if this register class may be used to create
88 : /// virtual registers.
89 0 : bool isAllocatable() const { return Allocatable; }
90 : };
91 :
92 : /// MCRegisterDesc - This record contains information about a particular
93 : /// register. The SubRegs field is a zero terminated array of registers that
94 : /// are sub-registers of the specific register, e.g. AL, AH are sub-registers
95 : /// of AX. The SuperRegs field is a zero terminated array of registers that are
96 : /// super-registers of the specific register, e.g. RAX, EAX, are
97 : /// super-registers of AX.
98 : ///
99 : struct MCRegisterDesc {
100 : uint32_t Name; // Printable name for the reg (for debugging)
101 : uint32_t SubRegs; // Sub-register set, described above
102 : uint32_t SuperRegs; // Super-register set, described above
103 :
104 : // Offset into MCRI::SubRegIndices of a list of sub-register indices for each
105 : // sub-register in SubRegs.
106 : uint32_t SubRegIndices;
107 :
108 : // RegUnits - Points to the list of register units. The low 4 bits holds the
109 : // Scale, the high bits hold an offset into DiffLists. See MCRegUnitIterator.
110 : uint32_t RegUnits;
111 :
112 : /// Index into list with lane mask sequences. The sequence contains a lanemask
113 : /// for every register unit.
114 : uint16_t RegUnitLaneMasks;
115 : };
116 :
117 : /// MCRegisterInfo base class - We assume that the target defines a static
118 : /// array of MCRegisterDesc objects that represent all of the machine
119 : /// registers that the target has. As such, we simply have to track a pointer
120 : /// to this array so that we can turn register number into a register
121 : /// descriptor.
122 : ///
123 : /// Note this class is designed to be a base class of TargetRegisterInfo, which
124 : /// is the interface used by codegen. However, specific targets *should never*
125 : /// specialize this class. MCRegisterInfo should only contain getters to access
126 : /// TableGen generated physical register data. It must not be extended with
127 : /// virtual methods.
128 : ///
129 94364 : class MCRegisterInfo {
130 : public:
131 : using regclass_iterator = const MCRegisterClass *;
132 :
133 : /// DwarfLLVMRegPair - Emitted by tablegen so Dwarf<->LLVM reg mappings can be
134 : /// performed with a binary search.
135 : struct DwarfLLVMRegPair {
136 : unsigned FromReg;
137 : unsigned ToReg;
138 :
139 0 : bool operator<(DwarfLLVMRegPair RHS) const { return FromReg < RHS.FromReg; }
140 : };
141 :
142 : /// SubRegCoveredBits - Emitted by tablegen: bit range covered by a subreg
143 : /// index, -1 in any being invalid.
144 : struct SubRegCoveredBits {
145 : uint16_t Offset;
146 : uint16_t Size;
147 : };
148 :
149 : private:
150 : const MCRegisterDesc *Desc; // Pointer to the descriptor array
151 : unsigned NumRegs; // Number of entries in the array
152 : unsigned RAReg; // Return address register
153 : unsigned PCReg; // Program counter register
154 : const MCRegisterClass *Classes; // Pointer to the regclass array
155 : unsigned NumClasses; // Number of entries in the array
156 : unsigned NumRegUnits; // Number of regunits.
157 : const MCPhysReg (*RegUnitRoots)[2]; // Pointer to regunit root table.
158 : const MCPhysReg *DiffLists; // Pointer to the difflists array
159 : const LaneBitmask *RegUnitMaskSequences; // Pointer to lane mask sequences
160 : // for register units.
161 : const char *RegStrings; // Pointer to the string table.
162 : const char *RegClassStrings; // Pointer to the class strings.
163 : const uint16_t *SubRegIndices; // Pointer to the subreg lookup
164 : // array.
165 : const SubRegCoveredBits *SubRegIdxRanges; // Pointer to the subreg covered
166 : // bit ranges array.
167 : unsigned NumSubRegIndices; // Number of subreg indices.
168 : const uint16_t *RegEncodingTable; // Pointer to array of register
169 : // encodings.
170 :
171 : unsigned L2DwarfRegsSize;
172 : unsigned EHL2DwarfRegsSize;
173 : unsigned Dwarf2LRegsSize;
174 : unsigned EHDwarf2LRegsSize;
175 : const DwarfLLVMRegPair *L2DwarfRegs; // LLVM to Dwarf regs mapping
176 : const DwarfLLVMRegPair *EHL2DwarfRegs; // LLVM to Dwarf regs mapping EH
177 : const DwarfLLVMRegPair *Dwarf2LRegs; // Dwarf to LLVM regs mapping
178 : const DwarfLLVMRegPair *EHDwarf2LRegs; // Dwarf to LLVM regs mapping EH
179 : DenseMap<unsigned, int> L2SEHRegs; // LLVM to SEH regs mapping
180 : DenseMap<unsigned, int> L2CVRegs; // LLVM to CV regs mapping
181 :
182 : public:
183 : /// DiffListIterator - Base iterator class that can traverse the
184 : /// differentially encoded register and regunit lists in DiffLists.
185 : /// Don't use this class directly, use one of the specialized sub-classes
186 : /// defined below.
187 : class DiffListIterator {
188 : uint16_t Val = 0;
189 : const MCPhysReg *List = nullptr;
190 :
191 : protected:
192 : /// Create an invalid iterator. Call init() to point to something useful.
193 205453848 : DiffListIterator() = default;
194 :
195 : /// init - Point the iterator to InitVal, decoding subsequent values from
196 : /// DiffList. The iterator will initially point to InitVal, sub-classes are
197 : /// responsible for skipping the seed value if it is not part of the list.
198 : void init(MCPhysReg InitVal, const MCPhysReg *DiffList) {
199 : Val = InitVal;
200 : List = DiffList;
201 : }
202 :
203 : /// advance - Move to the next list position, return the applied
204 : /// differential. This function does not detect the end of the list, that
205 : /// is the caller's responsibility (by checking for a 0 return value).
206 0 : unsigned advance() {
207 : assert(isValid() && "Cannot move off the end of the list.");
208 1729915197 : MCPhysReg D = *List++;
209 1729710670 : Val += D;
210 0 : return D;
211 : }
212 :
213 : public:
214 : /// isValid - returns true if this iterator is not yet at the end.
215 0 : bool isValid() const { return List; }
216 :
217 : /// Dereference the iterator to get the value at the current position.
218 544290423 : unsigned operator*() const { return Val; }
219 :
220 : /// Pre-increment to move to the next position.
221 : void operator++() {
222 : // The end of the list is encoded as a 0 differential.
223 637103267 : if (!advance())
224 252500480 : List = nullptr;
225 : }
226 : };
227 :
228 : // These iterators are allowed to sub-class DiffListIterator and access
229 : // internal list pointers.
230 : friend class MCSubRegIterator;
231 : friend class MCSubRegIndexIterator;
232 : friend class MCSuperRegIterator;
233 : friend class MCRegUnitIterator;
234 : friend class MCRegUnitMaskIterator;
235 : friend class MCRegUnitRootIterator;
236 :
237 : /// Initialize MCRegisterInfo, called by TableGen
238 : /// auto-generated routines. *DO NOT USE*.
239 : void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
240 : unsigned PC,
241 : const MCRegisterClass *C, unsigned NC,
242 : const MCPhysReg (*RURoots)[2],
243 : unsigned NRU,
244 : const MCPhysReg *DL,
245 : const LaneBitmask *RUMS,
246 : const char *Strings,
247 : const char *ClassStrings,
248 : const uint16_t *SubIndices,
249 : unsigned NumIndices,
250 : const SubRegCoveredBits *SubIdxRanges,
251 : const uint16_t *RET) {
252 94364 : Desc = D;
253 94364 : NumRegs = NR;
254 94364 : RAReg = RA;
255 94364 : PCReg = PC;
256 94364 : Classes = C;
257 94364 : DiffLists = DL;
258 94364 : RegUnitMaskSequences = RUMS;
259 94364 : RegStrings = Strings;
260 94364 : RegClassStrings = ClassStrings;
261 94364 : NumClasses = NC;
262 94364 : RegUnitRoots = RURoots;
263 94364 : NumRegUnits = NRU;
264 94364 : SubRegIndices = SubIndices;
265 94364 : NumSubRegIndices = NumIndices;
266 94364 : SubRegIdxRanges = SubIdxRanges;
267 94364 : RegEncodingTable = RET;
268 :
269 : // Initialize DWARF register mapping variables
270 52634 : EHL2DwarfRegs = nullptr;
271 52634 : EHL2DwarfRegsSize = 0;
272 52634 : L2DwarfRegs = nullptr;
273 52634 : L2DwarfRegsSize = 0;
274 52634 : EHDwarf2LRegs = nullptr;
275 52634 : EHDwarf2LRegsSize = 0;
276 52634 : Dwarf2LRegs = nullptr;
277 52634 : Dwarf2LRegsSize = 0;
278 : }
279 :
280 : /// Used to initialize LLVM register to Dwarf
281 : /// register number mapping. Called by TableGen auto-generated routines.
282 : /// *DO NOT USE*.
283 : void mapLLVMRegsToDwarfRegs(const DwarfLLVMRegPair *Map, unsigned Size,
284 : bool isEH) {
285 : if (isEH) {
286 91931 : EHL2DwarfRegs = Map;
287 91931 : EHL2DwarfRegsSize = Size;
288 : } else {
289 91931 : L2DwarfRegs = Map;
290 91931 : L2DwarfRegsSize = Size;
291 : }
292 : }
293 :
294 : /// Used to initialize Dwarf register to LLVM
295 : /// register number mapping. Called by TableGen auto-generated routines.
296 : /// *DO NOT USE*.
297 : void mapDwarfRegsToLLVMRegs(const DwarfLLVMRegPair *Map, unsigned Size,
298 : bool isEH) {
299 : if (isEH) {
300 91931 : EHDwarf2LRegs = Map;
301 91931 : EHDwarf2LRegsSize = Size;
302 : } else {
303 91931 : Dwarf2LRegs = Map;
304 91931 : Dwarf2LRegsSize = Size;
305 : }
306 : }
307 :
308 : /// mapLLVMRegToSEHReg - Used to initialize LLVM register to SEH register
309 : /// number mapping. By default the SEH register number is just the same
310 : /// as the LLVM register number.
311 : /// FIXME: TableGen these numbers. Currently this requires target specific
312 : /// initialization code.
313 : void mapLLVMRegToSEHReg(unsigned LLVMReg, int SEHReg) {
314 12394608 : L2SEHRegs[LLVMReg] = SEHReg;
315 : }
316 :
317 : void mapLLVMRegToCVReg(unsigned LLVMReg, int CVReg) {
318 12438142 : L2CVRegs[LLVMReg] = CVReg;
319 : }
320 :
321 : /// This method should return the register where the return
322 : /// address can be found.
323 0 : unsigned getRARegister() const {
324 0 : return RAReg;
325 : }
326 :
327 : /// Return the register which is the program counter.
328 0 : unsigned getProgramCounter() const {
329 0 : return PCReg;
330 : }
331 :
332 0 : const MCRegisterDesc &operator[](unsigned RegNo) const {
333 : assert(RegNo < NumRegs &&
334 : "Attempting to access record for invalid register number!");
335 605364722 : return Desc[RegNo];
336 : }
337 :
338 : /// Provide a get method, equivalent to [], but more useful with a
339 : /// pointer to this object.
340 : const MCRegisterDesc &get(unsigned RegNo) const {
341 498747195 : return operator[](RegNo);
342 : }
343 :
344 : /// Returns the physical register number of sub-register "Index"
345 : /// for physical register RegNo. Return zero if the sub-register does not
346 : /// exist.
347 : unsigned getSubReg(unsigned Reg, unsigned Idx) const;
348 :
349 : /// Return a super-register of the specified register
350 : /// Reg so its sub-register of index SubIdx is Reg.
351 : unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,
352 : const MCRegisterClass *RC) const;
353 :
354 : /// For a given register pair, return the sub-register index
355 : /// if the second register is a sub-register of the first. Return zero
356 : /// otherwise.
357 : unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;
358 :
359 : /// Get the size of the bit range covered by a sub-register index.
360 : /// If the index isn't continuous, return the sum of the sizes of its parts.
361 : /// If the index is used to access subregisters of different sizes, return -1.
362 : unsigned getSubRegIdxSize(unsigned Idx) const;
363 :
364 : /// Get the offset of the bit range covered by a sub-register index.
365 : /// If an Offset doesn't make sense (the index isn't continuous, or is used to
366 : /// access sub-registers at different offsets), return -1.
367 : unsigned getSubRegIdxOffset(unsigned Idx) const;
368 :
369 : /// Return the human-readable symbolic target-specific name for the
370 : /// specified physical register.
371 : const char *getName(unsigned RegNo) const {
372 74799101 : return RegStrings + get(RegNo).Name;
373 : }
374 :
375 : /// Return the number of registers this target has (useful for
376 : /// sizing arrays holding per register information)
377 0 : unsigned getNumRegs() const {
378 0 : return NumRegs;
379 : }
380 :
381 : /// Return the number of sub-register indices
382 : /// understood by the target. Index 0 is reserved for the no-op sub-register,
383 : /// while 1 to getNumSubRegIndices() - 1 represent real sub-registers.
384 0 : unsigned getNumSubRegIndices() const {
385 0 : return NumSubRegIndices;
386 : }
387 :
388 : /// Return the number of (native) register units in the
389 : /// target. Register units are numbered from 0 to getNumRegUnits() - 1. They
390 : /// can be accessed through MCRegUnitIterator defined below.
391 0 : unsigned getNumRegUnits() const {
392 0 : return NumRegUnits;
393 : }
394 :
395 : /// Map a target register to an equivalent dwarf register
396 : /// number. Returns -1 if there is no equivalent value. The second
397 : /// parameter allows targets to use different numberings for EH info and
398 : /// debugging info.
399 : int getDwarfRegNum(unsigned RegNum, bool isEH) const;
400 :
401 : /// Map a dwarf register back to a target register.
402 : int getLLVMRegNum(unsigned RegNum, bool isEH) const;
403 :
404 : /// Map a DWARF EH register back to a target register (same as
405 : /// getLLVMRegNum(RegNum, true)) but return -1 if there is no mapping,
406 : /// rather than asserting that there must be one.
407 : int getLLVMRegNumFromEH(unsigned RegNum) const;
408 :
409 : /// Map a target EH register number to an equivalent DWARF register
410 : /// number.
411 : int getDwarfRegNumFromDwarfEHRegNum(unsigned RegNum) const;
412 :
413 : /// Map a target register to an equivalent SEH register
414 : /// number. Returns LLVM register number if there is no equivalent value.
415 : int getSEHRegNum(unsigned RegNum) const;
416 :
417 : /// Map a target register to an equivalent CodeView register
418 : /// number.
419 : int getCodeViewRegNum(unsigned RegNum) const;
420 :
421 : regclass_iterator regclass_begin() const { return Classes; }
422 : regclass_iterator regclass_end() const { return Classes+NumClasses; }
423 : iterator_range<regclass_iterator> regclasses() const {
424 : return make_range(regclass_begin(), regclass_end());
425 : }
426 :
427 : unsigned getNumRegClasses() const {
428 : return (unsigned)(regclass_end()-regclass_begin());
429 : }
430 :
431 : /// Returns the register class associated with the enumeration
432 : /// value. See class MCOperandInfo.
433 0 : const MCRegisterClass& getRegClass(unsigned i) const {
434 : assert(i < getNumRegClasses() && "Register Class ID out of range");
435 577076 : return Classes[i];
436 : }
437 :
438 0 : const char *getRegClassName(const MCRegisterClass *Class) const {
439 98130 : return RegClassStrings + Class->NameIdx;
440 : }
441 :
442 : /// Returns the encoding for RegNo
443 0 : uint16_t getEncodingValue(unsigned RegNo) const {
444 : assert(RegNo < NumRegs &&
445 : "Attempting to get encoding for invalid register number!");
446 136487262 : return RegEncodingTable[RegNo];
447 : }
448 :
449 : /// Returns true if RegB is a sub-register of RegA.
450 : bool isSubRegister(unsigned RegA, unsigned RegB) const {
451 7816353 : return isSuperRegister(RegB, RegA);
452 : }
453 :
454 : /// Returns true if RegB is a super-register of RegA.
455 : bool isSuperRegister(unsigned RegA, unsigned RegB) const;
456 :
457 : /// Returns true if RegB is a sub-register of RegA or if RegB == RegA.
458 : bool isSubRegisterEq(unsigned RegA, unsigned RegB) const {
459 : return isSuperRegisterEq(RegB, RegA);
460 : }
461 :
462 : /// Returns true if RegB is a super-register of RegA or if
463 : /// RegB == RegA.
464 : bool isSuperRegisterEq(unsigned RegA, unsigned RegB) const {
465 8261 : return RegA == RegB || isSuperRegister(RegA, RegB);
466 : }
467 :
468 : /// Returns true if RegB is a super-register or sub-register of RegA
469 : /// or if RegB == RegA.
470 758 : bool isSuperOrSubRegisterEq(unsigned RegA, unsigned RegB) const {
471 544 : return isSubRegisterEq(RegA, RegB) || isSuperRegister(RegA, RegB);
472 : }
473 : };
474 :
475 : //===----------------------------------------------------------------------===//
476 : // Register List Iterators
477 : //===----------------------------------------------------------------------===//
478 :
479 : // MCRegisterInfo provides lists of super-registers, sub-registers, and
480 : // aliasing registers. Use these iterator classes to traverse the lists.
481 :
482 : /// MCSubRegIterator enumerates all sub-registers of Reg.
483 : /// If IncludeSelf is set, Reg itself is included in the list.
484 : class MCSubRegIterator : public MCRegisterInfo::DiffListIterator {
485 : public:
486 : MCSubRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
487 0 : bool IncludeSelf = false) {
488 106980902 : init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
489 : // Initially, the iterator points to Reg itself.
490 : if (!IncludeSelf)
491 : ++*this;
492 : }
493 : };
494 :
495 : /// Iterator that enumerates the sub-registers of a Reg and the associated
496 : /// sub-register indices.
497 : class MCSubRegIndexIterator {
498 : MCSubRegIterator SRIter;
499 : const uint16_t *SRIndex;
500 :
501 : public:
502 : /// Constructs an iterator that traverses subregisters and their
503 : /// associated subregister indices.
504 : MCSubRegIndexIterator(unsigned Reg, const MCRegisterInfo *MCRI)
505 : : SRIter(Reg, MCRI) {
506 1579565 : SRIndex = MCRI->SubRegIndices + MCRI->get(Reg).SubRegIndices;
507 : }
508 :
509 : /// Returns current sub-register.
510 : unsigned getSubReg() const {
511 : return *SRIter;
512 : }
513 :
514 : /// Returns sub-register index of the current sub-register.
515 0 : unsigned getSubRegIndex() const {
516 14800 : return *SRIndex;
517 : }
518 :
519 : /// Returns true if this iterator is not yet at the end.
520 : bool isValid() const { return SRIter.isValid(); }
521 :
522 : /// Moves to the next position.
523 : void operator++() {
524 : ++SRIter;
525 14800 : ++SRIndex;
526 : }
527 : };
528 :
529 : /// MCSuperRegIterator enumerates all super-registers of Reg.
530 : /// If IncludeSelf is set, Reg itself is included in the list.
531 : class MCSuperRegIterator : public MCRegisterInfo::DiffListIterator {
532 : public:
533 : MCSuperRegIterator() = default;
534 :
535 : MCSuperRegIterator(unsigned Reg, const MCRegisterInfo *MCRI,
536 : bool IncludeSelf = false) {
537 310917741 : init(Reg, MCRI->DiffLists + MCRI->get(Reg).SuperRegs);
538 : // Initially, the iterator points to Reg itself.
539 : if (!IncludeSelf)
540 : ++*this;
541 : }
542 : };
543 :
544 : // Definition for isSuperRegister. Put it down here since it needs the
545 : // iterator defined above in addition to the MCRegisterInfo class itself.
546 17755977 : inline bool MCRegisterInfo::isSuperRegister(unsigned RegA, unsigned RegB) const{
547 65631088 : for (MCSuperRegIterator I(RegA, this); I.isValid(); ++I)
548 53311384 : if (*I == RegB)
549 : return true;
550 12319704 : return false;
551 : }
552 :
553 : //===----------------------------------------------------------------------===//
554 : // Register Units
555 : //===----------------------------------------------------------------------===//
556 :
557 : // Register units are used to compute register aliasing. Every register has at
558 : // least one register unit, but it can have more. Two registers overlap if and
559 : // only if they have a common register unit.
560 : //
561 : // A target with a complicated sub-register structure will typically have many
562 : // fewer register units than actual registers. MCRI::getNumRegUnits() returns
563 : // the number of register units in the target.
564 :
565 : // MCRegUnitIterator enumerates a list of register units for Reg. The list is
566 : // in ascending numerical order.
567 : class MCRegUnitIterator : public MCRegisterInfo::DiffListIterator {
568 : public:
569 : /// MCRegUnitIterator - Create an iterator that traverses the register units
570 : /// in Reg.
571 : MCRegUnitIterator() = default;
572 :
573 0 : MCRegUnitIterator(unsigned Reg, const MCRegisterInfo *MCRI) {
574 : assert(Reg && "Null register has no regunits");
575 : // Decode the RegUnits MCRegisterDesc field.
576 222874014 : unsigned RU = MCRI->get(Reg).RegUnits;
577 222874014 : unsigned Scale = RU & 15;
578 222874014 : unsigned Offset = RU >> 4;
579 :
580 : // Initialize the iterator to Reg * Scale, and the List pointer to
581 : // DiffLists + Offset.
582 173591684 : init(Reg * Scale, MCRI->DiffLists + Offset);
583 :
584 : // That may not be a valid unit, we need to advance by one to get the real
585 : // unit number. The first differential can be 0 which would normally
586 : // terminate the list, but since we know every register has at least one
587 : // unit, we can allow a 0 differential here.
588 : advance();
589 : }
590 : };
591 :
592 : /// MCRegUnitMaskIterator enumerates a list of register units and their
593 : /// associated lane masks for Reg. The register units are in ascending
594 : /// numerical order.
595 : class MCRegUnitMaskIterator {
596 : MCRegUnitIterator RUIter;
597 : const LaneBitmask *MaskListIter;
598 :
599 : public:
600 : MCRegUnitMaskIterator() = default;
601 :
602 : /// Constructs an iterator that traverses the register units and their
603 : /// associated LaneMasks in Reg.
604 : MCRegUnitMaskIterator(unsigned Reg, const MCRegisterInfo *MCRI)
605 : : RUIter(Reg, MCRI) {
606 5980930 : uint16_t Idx = MCRI->get(Reg).RegUnitLaneMasks;
607 5980930 : MaskListIter = &MCRI->RegUnitMaskSequences[Idx];
608 : }
609 :
610 : /// Returns a (RegUnit, LaneMask) pair.
611 : std::pair<unsigned,LaneBitmask> operator*() const {
612 : return std::make_pair(*RUIter, *MaskListIter);
613 : }
614 :
615 : /// Returns true if this iterator is not yet at the end.
616 : bool isValid() const { return RUIter.isValid(); }
617 :
618 : /// Moves to the next position.
619 : void operator++() {
620 6339741 : ++MaskListIter;
621 : ++RUIter;
622 : }
623 : };
624 :
625 : // Each register unit has one or two root registers. The complete set of
626 : // registers containing a register unit is the union of the roots and their
627 : // super-registers. All registers aliasing Unit can be visited like this:
628 : //
629 : // for (MCRegUnitRootIterator RI(Unit, MCRI); RI.isValid(); ++RI) {
630 : // for (MCSuperRegIterator SI(*RI, MCRI, true); SI.isValid(); ++SI)
631 : // visit(*SI);
632 : // }
633 :
634 : /// MCRegUnitRootIterator enumerates the root registers of a register unit.
635 : class MCRegUnitRootIterator {
636 : uint16_t Reg0 = 0;
637 : uint16_t Reg1 = 0;
638 :
639 : public:
640 102726924 : MCRegUnitRootIterator() = default;
641 :
642 : MCRegUnitRootIterator(unsigned RegUnit, const MCRegisterInfo *MCRI) {
643 : assert(RegUnit < MCRI->getNumRegUnits() && "Invalid register unit");
644 181465067 : Reg0 = MCRI->RegUnitRoots[RegUnit][0];
645 157257058 : Reg1 = MCRI->RegUnitRoots[RegUnit][1];
646 : }
647 :
648 : /// Dereference to get the current root register.
649 0 : unsigned operator*() const {
650 1275182 : return Reg0;
651 : }
652 :
653 : /// Check if the iterator is at the end of the list.
654 0 : bool isValid() const {
655 0 : return Reg0;
656 : }
657 :
658 : /// Preincrement to move to the next root register.
659 0 : void operator++() {
660 : assert(isValid() && "Cannot move off the end of the list.");
661 163175552 : Reg0 = Reg1;
662 1533187 : Reg1 = 0;
663 0 : }
664 : };
665 :
666 : /// MCRegAliasIterator enumerates all registers aliasing Reg. If IncludeSelf is
667 : /// set, Reg itself is included in the list. This iterator does not guarantee
668 : /// any ordering or that entries are unique.
669 : class MCRegAliasIterator {
670 : private:
671 : unsigned Reg;
672 : const MCRegisterInfo *MCRI;
673 : bool IncludeSelf;
674 :
675 : MCRegUnitIterator RI;
676 : MCRegUnitRootIterator RRI;
677 : MCSuperRegIterator SI;
678 :
679 : public:
680 102726924 : MCRegAliasIterator(unsigned Reg, const MCRegisterInfo *MCRI,
681 : bool IncludeSelf)
682 102726924 : : Reg(Reg), MCRI(MCRI), IncludeSelf(IncludeSelf) {
683 : // Initialize the iterators.
684 206978692 : for (RI = MCRegUnitIterator(Reg, MCRI); RI.isValid(); ++RI) {
685 104260111 : for (RRI = MCRegUnitRootIterator(*RI, MCRI); RRI.isValid(); ++RRI) {
686 212341229 : for (SI = MCSuperRegIterator(*RRI, MCRI, true); SI.isValid(); ++SI) {
687 108072775 : if (!(!IncludeSelf && Reg == *SI))
688 : return;
689 : }
690 : }
691 : }
692 : }
693 :
694 858801827 : bool isValid() const { return RI.isValid(); }
695 :
696 : unsigned operator*() const {
697 : assert(SI.isValid() && "Cannot dereference an invalid iterator.");
698 782151073 : return *SI;
699 : }
700 :
701 794297853 : void advance() {
702 : // Assuming SI is valid.
703 : ++SI;
704 794297853 : if (SI.isValid()) return;
705 :
706 : ++RRI;
707 161642365 : if (RRI.isValid()) {
708 94826 : SI = MCSuperRegIterator(*RRI, MCRI, true);
709 47413 : return;
710 : }
711 :
712 : ++RI;
713 161594952 : if (RI.isValid()) {
714 147589722 : RRI = MCRegUnitRootIterator(*RI, MCRI);
715 73794861 : SI = MCSuperRegIterator(*RRI, MCRI, true);
716 : }
717 : }
718 :
719 765608489 : void operator++() {
720 : assert(isValid() && "Cannot move off the end of the list.");
721 794297946 : do advance();
722 794297857 : while (!IncludeSelf && isValid() && *SI == Reg);
723 765608400 : }
724 : };
725 :
726 : } // end namespace llvm
727 :
728 : #endif // LLVM_MC_MCREGISTERINFO_H
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